NDS355 查看數據表（PDF） - Fairchild Semiconductor
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NDS355 Datasheet PDF : 7 Pages
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March 1996
NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMICA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.6A, 30V. RDS(ON) = 0.125Ω @ VGS = 4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage - Continuous
ID
Drain Current - Continuous
- Pulsed
(Note 1a)
PD
Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to -Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS355N
30
20
± 1.6
± 10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS355N Rev. D1
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