NE5562 查看數據表（PDF） - Philips Electronics
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NE5562 Datasheet PDF : 29 Pages
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Philips Semiconductors
Switched-mode power supply control circuit
Product specification
NE/SE5562
FEED-
FORWARD
1
+
+
VZ
+7.50V
3
2
1
CT
CURRENT
STEERING
IO
(5.25V)
–
VH
R2
28k
+
(1.70V)
R3
–
3k
+
EXT.
SYNC
11
ACTIVE LOW
0.8V
S
FF
R
TIME BASE
SIGNAL
TO DELAY
CIRCUIT
SAWTOOTH
GENERATOR
DISCH.
VOLTAGE
FEEDBACK
8
+3.80V
ERROR
AMP
+
–
–
–
–
10
PWM
COMPARATOR
Figure 14.
OUTPUT TO
LATCH RESET
SL00401
THE NE/SE5562 THEORY OPERATION
The Sawtooth Oscillator
The sawtooth oscillator consists of a gated charge-discharge
capacitor circuit with threshold comparators setting the peak and
valley voltages of the ramp. The resistor divider R1-3 is supplied
with a source voltage derived from either VZ (7.50V) minus two
diode drops, or, when feed-forward is in control, a voltage greater
than VZ and proportional to the main supply voltage. The nominal
upper threshold voltage is 5.25V and the lower threshold 1.70V.
These then determine the sawtooth peak and valley voltages,
respectively.
Operation
Beginning with the charge cycle, ramp voltage builds up on the
timing capacitor due to a constant current supplied to the node at
Pin 2. When capacitor voltage reaches the upper threshold,
comparator A switches, setting the latching flip-flop. The output of
the latch goes high, generating a clock pulse. The discharge
transistor is simultaneously turned on, reducing charge on the timing
capacitor to the point at which the lower threshold voltage, 1.70V, is
reached. The lower comparator is then activated, resetting the latch
and terminating the clock pulse. Note that the discharge transistor is
referenced to the same return diodes as the threshold resistor
divider and the discharge current is made to track with the charge
current. This charge and discharge tracking results in a true
sawtooth waveform even at extended frequencies. Figure 17 shows
a family of curves which explains the relationship between RT, CT,
and the frequency of the sawtooth generator. The data sheet shows
the initial accuracy of the oscillator at 60Hz and 600kHz.
THE PULSE WIDTH MODULATOR AND ERROR
AMPLIFIER
The PWM consists of a multi-input voltage comparator (Figure 15)
having its positive input tied to the sawtooth ramp voltage and the
various negative inputs referenced to ORed control signal nodes.
The primary control signal is the error amplifier output voltage node
which sets the active duty cycle termination point of the PWM output
waveform. As the error amplifier input signal derived from the power
supply load voltage varies, for instance in a negative direction, the
amplifier output moves upward, raising the PWM comparator toward
longer duty cycles at the output on Pin 19. The start-up sequence
begins with zero voltage at the input to the error amplifier. Since this
could signal an open feedback loop, the loop fault comparator on
Pin 8 clamps the PWM duty cycle until the feedback voltage
exceeds 0.955V. A second comparator monitors the duty cycle
control, Pin 5, with the same threshold level, inhibiting the output via
the start-stop latch (Figure 16).
The charging of the slow-start capacitor provides a controlled
ramp-up of the output duty cycle and a resultant gradual increase in
energy fed to the output magnetics.
The dynamic response of the PWM comparator is shown in the
simulated waveform drawing of Figure 17. The error amplifier output
voltage is depicted as sloping positive (increasing) with time as
referenced to the sawtooth waveform. This causes the duty cycle to
increase with time. This is an indication of an increasing load on the
power supply as output voltage is decreasing. The Pin 5 (δMAX)
control voltage is also superimposed midway on the sawtooth,
indicating the limits of duty cycle increase as the output waveform
no longer increases in duty cycle after the δMAX threshold is
crossed. A hypothetical overcurrent pulse (Pin 14) is shown to
illustrate cycle termination immediately at the output (Pin 19).
1994 Aug 31
10
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