EVAL-AD7470CB(2000) 查看數據表（PDF） - Analog Devices
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EVAL-AD7470CB Datasheet PDF : 16 Pages
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AD7470/AD7472
TIMING SPECIFICATIONS1
(VDD = +2.7 V to +5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
AD7470
AD7472
Units
Description
fCLK 2
tCONVERT
tWAKEUP
t1
t23
t3
t44
t5
t64
t75
t8
t9
t10
10
30
436.42
1
10
10
30
0
0
20
15
8
0
135
100
10
26
531.66
1
10
10
30
0
0
20
15
8
0
135
100
kHz min
MHz max
ns min
µs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
tCLK = 1/fCLK IN
Wake-Up Time
CONVST Pulsewidth
CONVST to BUSY Delay, VDD = 5 V
CONVST to BUSY Delay, VDD = 3 V
BUSY to CS Setup Time
CS to RD Setup Time
RD Pulsewidth
Data Access Time After Falling Edge of RD
Bus Relinquish Time After Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See
Figure 1.
2Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST.
3t2 is 35 ns max @ +125°C.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
IOL
TO OUTPUT
PIN
CL
50pF
200A
IOH
+1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. A
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