NIS5135(2013) 查看數據表（PDF） - ON Semiconductor

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NIS5135
(Rev.:2013)

+5 Volt Electronic Fuse

ON Semiconductor 

NIS5135 Series

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 5.0 V, CL = 70 mF, dv/dt pin open, RLIMIT= 10 W, TJ = 25°C

unless otherwise noted.)

Characteristics

Symbol

Min

Typ

Max

Unit

POWER FET

Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load)

Tdly

ON Resistance (Note 4)

TJ = 140°C (Note 5)

RDSon

54

Off State Output Voltage

Voff

(VCC = 10 Vdc, VGS = 0 Vdc, RL = R)

Output Capacitance

Cout

VDS = 5 VDC, VGS = 0 VDC, RL = R

Continuous Current (TA = 25°C, 0.5 in2 pad) (Note 5)

ID

(TA = 80°C, minimum copper)

ID

THERMAL LATCH

500

ms

68

82

mW

95

50

200

mV

230

pF

3.6

A

1.7

Shutdown Temperature (Note 5)

TSD

150

175

200

°C

Thermal Hysteresis (Decrease in die temperature for turn on, does not

apply to latching parts)

THyst

45

°C

UNDER/OVERVOLTAGE PROTECTION

VOUT Maximum (VCC = 10 V)

Undervoltage Lockout (Turn on, Voltage Going High)

UVLO Hysteresis

CURRENT LIMIT

Vout−clamp

5.95

6.65

7.35

V

VUVLO

3.2

3.6

4.0

V

VHyst

−

0.40

−

V

Kelvin Short Circuit Current Limit (RLimit = 11 W, Note 6)

Kelvin Overload Current Limit (RLimit = 11 W, Note 6)

dv/dt Circuit

ILIM

2.3

3.1

3.9

A

ILIM

3.5

A

Output Voltage Ramp Time (Enable to VOUT = 4.7 V)

Maximum Capacitor Voltage

ENABLE/FAULT

tslew

0.70

1.4

2.4

ms

Vmax

VCC

V

Logic Level Low (Output Disabled)

Logic Level Mid (Thermal Fault, Output Disabled)

Logic Level High (Output Enabled)

High State Maximum Voltage

Logic Low Sink Current (Venable = 0 V)

Logic High Leakage Current for External Switch (Venable = 3.3 V)

Maximum Fanout for Fault Signal (Total number of chips that can be

connected to this pin for simultaneous shutdown)

Vin−low

Vin−mid

Vin−high

Vin−max

Iin−low

Iin−leak

Fan

0.35

0.82

1.96

3.40

0.58

1.4

2.64

4.30

−12

0.81

V

1.95

V

3.30

V

5.2

V

−20

mA

1.0

mA

3.0

Units

TOTAL DEVICE

Bias Current (Operational)

IBias

Bias Current (Shutdown)

IBias

Minimum Operating Voltage (Notes 5 and 7)

Vmin

4. Pulse test: Pulse width 300 ms, duty cycle 2%.

5. Verified by design.

6. Refer to explanation of short circuit and overload conditions in application note AND8140/D.

7. Device will shut down prior to reaching this level based on actual UVLO trip point.

1.5

2.0

mA

1.0

mA

3.1

V

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