NJ88C25 查看數據表（PDF） - Zarlink Semiconductor Inc
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NJ88C25 Datasheet PDF : 8 Pages
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NJ88C25
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated:
VDD–VSS=2·7V to 5·5V. Temperature range = –30°C to +70°C
DC Characteristics
Characteristic
Min.
Value
Typ. Max.
Units
Supply current
5·5
mA
0·7
mA
3·7
mA
OUTPUTS
Modulus Control (MC), BAND 1 and BAND 2
High level
Low level
VDD20·4
V
0·4
V
Lock Detect (LD) and FV
Low level
0·4
V
Open drain pull-up voltage
7·0
V
PDB
High level
4·6
V
Low level
0·4
V
3-state leakage current
±0·1 µA
Conditions
fosc, fFIN = 20MHz
fosc, fFIN = 1MHz
fosc, fFIN = 10MHz
0 to 5V
square
wave
ISOURCE = 1mA
ISINK = 1mA
ISINK = 4mA
ISOURCE = 4mA
ISINK = 4mA
AC Characteristics
Characteristic
Value
Min. Typ. Max.
Units
Conditions
FIN and OSC IN input level
Max. operating frequency, fFIN and fosc
Propagation delay, clock to modulus control MC
Programming Inputs
Clock high time, tCH
Clock low time, tCL
Enable set-up time, tES (see note 5)
Enable hold time, tEH
Data set-up time, tDS
Data hold time, tDH
Clock rise and fall times
Positive threshold
Negative threshold
Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Programming capacitor, CAP
Output resistance, PDA
200
20
30 50
0·5
0·5
0·2
tCH
0·2
0·2
0·2
0·2
3
2
500
5
1
1
5
mV RMS 10MHz AC-coupled sinewave
MHz
ns
Input squarewave VDD to VSS,
See note 2
µs
µs
All timing periods
µs
are referenced to
µs
the negative
µs
transition of the
µs
clock waveform.
µs
See note 5
V
TTL compatible, see note 1
V
ns
kΩ
nF
See note 3
nF
kΩ
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and
FIN inputs.
5. Clock to enable set-up time (tES) is variable, dependent on fOSC. It needs to be specified in terms of fOSC, clock high time (tCH) and clock low time
(tCL) and must meet the following conditions: 431/fOSC<tES,(tCH1tCL).
2
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