NJU26123V 查看數據表（PDF） - Japan Radio Corporation

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NJU26123V

Digital Signal Processor for TV

Japan Radio Corporation  

NJU26123

Table 6

Mode

DSP

Slave

Input clock (In Slave mode)

Clock Signal

Multiple Frequency

32kHz

44.1kHz

48kHz

LR

1fs

32kHz

44.1kHz

48kHz

BCK (32fs)

32fs

1.024MHz 1.4112MHz 1.536MHz

BCK (64fs)

64fs

2.048MHz 2.822MHz 3.072MHz

MCK

(SLAVEb=”L”)

Input terminal: Clock is generated by MCK or CLK

MCK

(SLAVEb=”H”)

Buffer output of CLK

12.288MHz

Table 7 Output clock (In Master mode)

Mode Clock Signal

Multiple Frequency

DSP

Master

LR

BCK (32fs)

BCK (64fs)

MCK

1fs

32fs

64fs

Buffer output of CLK

CLK pin frequency

32kHz

44.1kHz

48kHz

32kHz

-

48kHz

1.024MHz

-

1.536MHz

2.048MHz

-

3.072MHz

12.288MHz

- 10 -

Ver.2008-04-17

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