NJU26123V 查看數據表（PDF） - Japan Radio Corporation
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NJU26123V Datasheet PDF : 19 Pages
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NJU26123
■ Pin Configuration
RESETb
1
LR
2
BCK
3
SDI2
4
SDI1
5
SDI0
6
MCK
7
VDD
8
VSS
9
STBYb
10
VSS
11
VREGO
12
NJU26123
SSOP24
24
TEST
23
SCL
22
SDA
21
SDO2
20
SDO1
19
SDO0
18
WDC
17
PROC
16
AD1
15
SLAVEb
14
CLK
13
CLKOUT
■ Pin Description
Fig. 3 NJU26123 Pin Configuration
Table 1 Pin Description
No. Symbol I/O Description
No. Symbol I/O Description
1 RESETb I
RESET (active Low)
13 CLKOUT O OSC Output
2 LR
I/O LR Clock
14 CLK
I OSC Clock Input
3 BCK
4 SDI2
I/O Bit Clock
I
Audio Data Input 2 L/R
15 SLAVEb I
16 AD1
I
Slave select
I2C Address
5 SDI1
I
Audio Data Input 1 L/R
17 PROC
I Status select after Reset DSP
6 SDI0
I
Audio Data Input 0 L/R
18 WDC
OD Clock for Watch Dog Timer
7 MCK
I/O Master Clock
19 SDO0
O Audio Data Output 0 L/R
8 VDD
- Power Supply +3.3V
20 SDO1
O Audio Data Output 1 L/R
9 VSS
-
10 STBYb I
11 VSS
-
GND
For TEST (Connected to VDD)
GND
21 SDO2
22 SDA
23 SCL
O Audio Data Output 2 L/R
OD I2C I/O
I
I2C Clock
12 VREGO PI Built-in Power Supply Bypass
24 TEST
I For TEST(Connected to VSS)
* I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass
AD1 (No.16) pin and PROC (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance.
However, these pins operate as bi-directional pins. No.16pin and No.17pin connect with VDD or VSS through 3.3kΩ
resistance. No.18pin do not connect or connect with VDD through 3.3kΩ resistance when unused.
VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel
between VSS (No.11) pin. A built-in power supply is used only for NJU26123 operation. Be not short-circuited of this pin.
Do not take out the current, and connect other power supplies.
-4-
Ver.2008-04-17
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