NJU26123V 查看數據表（PDF） - Japan Radio Corporation

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NJU26123V

Digital Signal Processor for TV

Japan Radio Corporation  

NJU26123

■ Electric Characteristics

Table 3 Electric Characteristics

Parameter

Symbol

Test Condition

Operating Voltage *1

Operating Current

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage *3

Low Level Output Voltage

Leakage Current *4

Clock Frequency

Clock Jitter *5

Clock Duty Cycle

VDD

IDD

VIH

VIL

VOH

VOL

IIN

IIN(PU)

IIN(PD)

fOSC

fJIT(CC)

rEC

VDD pin

At no load

(IOH= -1mA)

(IOL= 1mA)

VIN = VSS to VDD

CLK, MCK *6

( VDD=3.3V, fOSC=12.288MHz, Ta=25°C )

Min.

Typ.

Max.

Units

3.0

3.3

3.6

V

-

20

35

mA

VDD x 0.7

-

VDD *2

0

-

VDD x 0.8

-

VDD x 0.3

V

VDD

0

-

VDD x 0.2

-10

-

10

-120

-

10

µA

-10

-

120

10

12.288

13

MHz

0

-

3.0

ns

45

50

55

%

*1

*2 Input pin, Output pin and Open-Drain input/output pin are +5.0V tolerant except CLK input pin.

*3 Except No.18pin: WDC (Open-Drain output) and No.22: SDA (Open-Drain input/output).

*4 I IN(PU) : 18pin, I IN(PD) : 15, 16, 17, 24 pin

*5 Clock Jitter shows Cycle-to-cycle period jitter (JEDEC JESD65).

*6 Provide clock frequency for fOSC spec. NJU26123 needs clock frequency 12.288MHz when sampling rate is 48kHz.

-6-

Ver.2008-04-17

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