NJU26123V 查看數據表（PDF） - Japan Radio Corporation

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NJU26123V

Digital Signal Processor for TV

Japan Radio Corporation  

NJU26123

1. Power Supply, Input/Output terminal, Clock, Reset

1.1 Power Supply

The NJU26123 has a power supply VDD. To setup good power supply condition, the decoupling capacitors

should be implemented at the all power supply terminals.

The NJU26123 include a built-in power supply (LDO) for internal logic. A built-in power supply generates

1.8V (-10% to +10%). VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR

capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin.

A built-in power supply is used only for NJU26123 operation. Be not short-circuited of this pin. Do not take

out the current, and connect other power supplies.

1.2 Input/Output terminal

It restricts, when the input terminals (AD1, PROC, RESETb, SDI0, SDI1, SDI2, STBYb, SLAVEb, SCL,

TEST pins), the input/output terminals (LR, BCK, MCK pins) and the bi-directional Open-drain terminal

(SDA pin) of NJU26123, and VDD are supplied on regular voltage (VDD=3.3V), and it becomes +5V Input

tolerant.

1.3 Clock

The NJU26123 CLK pin requires the system clock that should be related to the sample frequency 256 Fs.

(For example : Fs=48kHz CLK=12.288MHz )

It is possible to be generated the system clock by connecting a crystal oscillator between CLK and

CLKOUT. CLK/CLKOUT pins are not 5V tolerant, so check the voltage level of these pins.

When SLAVEb pin is fixed on Low level, NJU26123 supplies the system clock from MCK pin. Fix the clock

input pin not used to Low level because either the CLK pin or the MCK pin is supplied in NJU26123.

The frequency divider for Master mode matched to the clock 256 times of Fs is installed in NJU26123.

When clock except 256 times of Fs is used by Master mode, be careful to use because a dividing

frequency of Master mode changes. Please check enough and decide parameter.

Ver.2008-04-17

-7-

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