NJU26123V 查看數據表（PDF） - Japan Radio Corporation

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产品描述 (功能)

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NJU26123V

Digital Signal Processor for TV

Japan Radio Corporation  

NJU26123

2. Digital Audio Clock

Digital audio data needs to synchronize and transmit between digital audio systems.

The NJU26123 - master mode / slave mode - both of the modes are supported.

- In Master mode;

Use the clock of BCKO and a LRO pin output clock for digital audio data transfer.

- In Slave mode;

The clock output from a master device is needed for the input terminal of BCKI and LRI.

A device in the system generates the transmitted clock become a standard. The other devices are set

according to the transmitted clock. The device generating transmitted clock is called Master Device. The

device according to the transmitted clock is called Slave Device. NJU26123 usually operates Slave Device.

However, NJU26123 becomes Master Device in case of SLAVEb set the High level and NJU26123 is set

Master mode by firmware command. In Slave mode, clock inputted to the BCK pin and the LR pin is used

to digital audio signal transmission. In Master mode, clock outputted to the BCK pin and the LR pin is used

to digital audio signal transmission.

2.1 Audio Clock

Three kinds of clocks are needed for digital audio data transfer.

(1) LR clock (LR) is needed by serial-data transmission. It is the same as the sampling

frequency of a digital audio signal.

(2) Bit clock (BCK) is needed by serial-data transmission. It becomes the multiple of LR clock.

(3) Master clock (MCK) is needed by A/D, D/A converter, etc. It becomes the multiple of LR

clock. It is not related to serial audio data transmission.

In SLAVEb is High level, the MCK pin becomes buffer output pin for input clock to the CLK pin after

NJU26123 resets. The MCK output is able to be stopped by firmware command.

In SLAVEb is Low level, MCK pin becomes system clock input pin. It is not insure to change the logical

switch of SLAVEb pin during operating. If it is necessary to change SLAVEb pin setting, reset NJU26123

every time.

Table 5 SLAVEb, BCK, LR, MCK

SLAVEb and firmware

setting

LR pin

SLAVEb=”Low”

Firmware: each

SLAVEb=”H”

Firmware: Slave

LR clock input

DSP slave operating

SLAVEb=”H”

Firmware: Master

LR clock output

DSP Master operating

BCK pin

Bit clock input

DSP slave operating

Bit clock output

DSP Master

operating

MCK pin

NJU26123 operating clock input

(MCK or CLK)

Master clock output

(Buffer of CLK)

In NJU26123 is used by 256 times of Maximum sampling frequency, NJU26123 is able to output LR clock

of same sampling rate and two-third times of sampling rate, and output BCK clock of 32 times sampling

rate and 64 times sampling rate in Master mode.

Ver.2008-04-17

-9-

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