NJU3430 查看數據表（PDF） - Japan Radio Corporation

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NJU3430

16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER

Japan Radio Corporation  

NJU3430

(2)Reset Function

(2-1)Initialization by Reset Terminal

The NJU3430 incorporates RST terminal to initialize the all system. When the "L" level is input over 1us to the

RST terminal, the reset sequence is executed. The Initialization flow is shown below :

Each RAM Address

Each RAM Data

Output Port

Display Digits

Contrast Control

All Display ON/OFF

--- (00)H

--- Unfixed

--- "L" Level (VSS)

--- 16-digit

--- 8/16 Duty

--- All Display OFF

(2-2)Initialization (After the Reset)

Reset

↓

Display Digits Set

↓

Contrast Control Set

↓

DD RAM Address Set → Data Writing

↓

CG RAM Address Set → Data Writing

↓

MK RAM Address Set → Data Writing

↓

Output Port Set

↓

All Display Off

← (Initialization : 16-digit)

← (Initialization : 8/16 Duty)

← Data set should be executed because

the data in DD RAM is unfixed.

← Data set should be executed because

the data in CG RAM is unfixed.

← Data set should be executed because

the data in MK RAM is unfixed.

← (Initialization : All “Low” level)

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