NJU6543 查看數據表（PDF） - Japan Radio Corporation

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产品描述 (功能)

生产厂家

NJU6543

1/2 1/3 1/4 Duty LCD Driver

Japan Radio Corporation  

Preliminary NJU6543

(2) Serial Data Transfer

The transfer of an 8-bit/word serial data is conducted by synchronizing clock via interface with CPU. During

CSb=”L”, serial data is obtainable and will be read in at the rising edge of SCK signal.

After CSb becoming low, by the first word, address data is distinguished by D7 and D6.

In the case of address data(D7,D6=”0,1”), the 2nd data can be transferred continually and interrupted as

display data even if CSb maintained low. In this case, every 8-bits data will be confirmed as a word either by

the falling edge of the8th SCK clock or by the rising edge of the CSb clock.

After CSb becoming low, if the first word is command data(D7,D6=”1,0”or “1,1”), the after data is invalid even

though transfer can be continued without changing the polarity of CSb.( Effective the first word)

At the falling edge of CSb, SCK can be either “H” or “L”, but, at the rising edge of CSb, SCK must be low.

Command data

CSb

At this rising edge, one word is confirmed

SCK

SI

D7 D6 D5 D4 D3 D2 D1 D0

Timing of Serial Data Transfer

SCK and SI (Address data and display data)

At this rising edge of CSb, when

SCK=”Lo”, one word is confirmed.

CSb

SCK

SI

WORD 1

WORD2

Serial Interface Format

WORD n

Ver.2008-11-28

-5-

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