NJW1109V 查看數據表（PDF） - Japan Radio Corporation
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NJW1109V Datasheet PDF : 14 Pages
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NJW1109
s DEFINITION OF I2C REGISTER
q I2C BUS FORMAT
MSB
LSB MSB
LSB MSB
S
Slave Address
A
Select Address
A
1bit
8bit
1bit
8bit
1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
q SLAVE ADDRESS
MSB
1
0
0
0
0
0
0
1
0
0
0
0
1
0
q SELECT ADDRESS
The auto-increment function cycles the select address as follows.
00H→01H→00H
Select
Address
D7
D6
D5
D4
BIT
D3
00H
VOL
01H
CHS
BAL
!CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
Select
BIT
Address
D7
D6
D5
D4
D3
00H
0
0
0
0
0
01H
0
0
0
0
0
!CONTROL COMMAND TABLE
a) Master Volume
Select
Address
D7
D6
D5
00H
•VOL : Master Volume
Attenuation level : +20 to –80dB(0.5dB/step), MUTE
BIT
D4
D3
VOL
b) Balance
Select
Address
D7
D6
D5
D4
01H
CHS
BAL
•CHS : Balance channel select
“0” : Ach “Bch is attenuated”
“1” : Bch “Ach is attenuated”
•BAL : Ach and Bch Ach and Bch Balance
Balance Level : 0 to –30dB (1dB/Step) , MUTE
BIT
D3
Data
8bit
LSB
AP
1bit 1bit
LSB
0
0
80H (ADR = Low)
84H (ADR = High)
D2
D1
D0
Don’t Care
D2
D1
D0
0
0
0
0
0
0
D2
D1
D0
D2
D1
D0
Don’t Care
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