NT5DS16M16CS 查看數據表（PDF） - NanoAmp Solutions, Inc.

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NT5DS16M16CS

256Mb DDR Synchronous DRAM

NanoAmp Solutions, Inc. 

NanoAmp Solutions, Inc.

Block Diagram (32Mb x 8)

NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT

NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS

CKE

CK

CK

CS

WE

CAS

RAS

Mode

Registers

13

15

13

A0-A12,

BA0, BA1

15

2

2

10 Column-Address

Counter/Latch

Bank3

Bank1 Bank2

CK, CK

DLL

8192

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

I/O Gating

DM Mask Logic

512

(x16)

Column

Decoder

9

COL0

1

16

16

16

Data

8

8

8

DQS

Generator

COL0 Input

Register

Write Mask 1

1

FIFO

&

Drivers

1

2

16 8

1

8

clk

out

clk

in

Data

8

8

1

DQS

1

8

CK,

COL0

CK

1

DQ0-DQ7,

DM

DQS

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

DOC # 14-02-044 Rev A ECN # 01-1116

6

The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com

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