NTE3881 查看數據表（PDF） - NTE Electronics

零件编号

产品描述 (功能)

生产厂家

NTE3881

Integrated Circuit NMOS, Parallel I/O Interface (PIO), 4MHz

NTE Electronics 

DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified)

Parameter

Symbol

Test Conditions

Min Typ Max Unit

Clock Input Low Voltage

Clock Input High Voltage

VILC

VIHC

–0.3 – 0.80 V

VCC–0.6 – VCC+3 V

Input Low Voltage

VIL

–0.3 – 0.8 V

Input High Voltage

VIH

2.0

– VCC V

Output Low Voltage

Output High Voltage

Power Supply Current

Input Leakage Current

Tri–State Output Leakage Current in Float

Tri–State Output Leakage Current in Float

Data Bus Leakage Current in Input Mode

Darlington Drive Current

VOL

VOH

ICC

IL1

ILOH

ILOL

ILD

IOHD

IOL = 2.0mA

IOH = –250µA

VIN = 0 to VCC

VOUT = 2.4 to VCC

VOUT = 0.4V

0 ≤ VIN ≤ VCC

VOH = 1.5V Port B Only

–

– 0.4 V

2.4

–

–

V

–

–

70 mA

–

– ±10 µA

–

–

10 µA

–

– –10 µA

–

– ±10 µA

–1.5 –

– mA

Capacitance: (TA = +25°C, f = 1MHz unless otherwise specified)

Parameter

Symbol

Test Conditions

Clock Capacitance

Input Capacitance

Output Capacitance

Cφ

CIN

COUT

Unmeasured Pins

Input Capacitance

Min Typ Max Unit

– – 10 pF

––

5 pF

– – 10 pF

AC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified)

Parameter

Symbol

Test Conditions Min Typ Max Unit

Clock Cycle Time

TcC

Note 1

250 –

– ns

Clock Width (High)

TcCH

105 – 2000 ns

Clock Width (Low)

TcCL

105 – 2000 ns

Clock Fall Time

TfC

– – 30 ns

Clock Rise Time

TrC

– – 30 ns

CE, B/A, C/E, to RD, IORQ ↓ Setup Time

TsCS(RI) Note 2

50 –

– ns

Any Hold Time for Specified Setup Time

Th

0–

– ns

RD, IORQ to Clock ↑ Setup Time

TsRI(C)

115 –

– ns

RD, IORQ ↓ to Data Out Delay

TdRI(DO) Note 3

– – 380 ns

RD, IORQ ↑ to Data Out Float Delay

TdRI(DOr)

– – 110 ns

Data In to Clock ↑ Setup Time

IORQ ↓ to Data Out Delay (INTA Cycle)

TsDI(C) CL = 50pF

TdIO(DOI) Note 4

50 –

250 –

– ns

– ns

M1 ↓ to Clock ↑ Setup Time

TsM1(Cr)

90 –

– ns

M1 ↑ to Clock ↓ Setup Time (M1 Cycle)

TsM1(Cf)

0–

– ns

Note 1 TcC = TwCh + TwCI + TrC + TfC.

Note 2. TsCS(RI) may be reduced. However, the time subtracted from TsCS(RI) will be added to

TdR(DO).

Note 3. Increase TdRI(DO) by 10ns for each 50pF increase in loading up to 200pF max.

Note 4. Increase TdIO(DOT) by 10ns for each 60pF increase in loading up to 200pF max.

Share Link: