NTE3881 查看數據表（PDF） - NTE Electronics
零件编号
产品描述 (功能)
生产厂家
NTE3881 Datasheet PDF : 4 Pages
| |||
AC Characteristics (Cont’d): (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified)
Parameter
Symbol
Test Conditions Min Typ Max Unit
M1 ↓ to IEO ↓ Delay (Interrupt Immediately
Preceding M1)
TdM1(IEO) Note 5, Note 6
– – 190 ns
IEI to IORQ ↓ Setup Time (INTA Cycle)
TsIE(IO) Note 6
140 –
– ns
IEI ↓ to IEO ↓ Delay
IEI ↑ to IEO ↑ Delay (after ED Decode)
TdIEI(IEO) CL = 50pF, Note 5
TdIE(IIOr) Note 5
– – 130 ns
– – 160 ns
IORQ ↑ to Clock ↓ Setup Time (To Activate
READY on Next Clock Cycle)
TsIO(C)
220 –
– ns
Clock ↓ to Ready ↑ Delay
Clock ↓ to Ready ↓ Delay
TdC(RDYr) CL = 50pF, Note 5
TdC(RDYf) Note 5
200 –
150 –
– ns
– ns
STROBE Pulse Width
TwSTB Note 4
150 –
– ns
STROBE ↑ to Clock ↓ Setup Time (To Activate
READY on Next Clock Cycle)
TsSTB(C)
200 –
– ns
IORQ ↑ to PORT Data Stable Delay (Mode 0)
TdIO(PD) Note 5
– – 180 ns
PORT DATA to STROBE ↑ Setup Time (Mode 1) TsPD(STB)
230 –
– ns
STROBE ↓ to PORT DATA Stable (Mode 2)
TdSTB(PD) Note 5
– – 210 ns
STROBE ↑ to PORT DATA Float Delay (Mode 2) TdSTB(PDz) CL = 50pF
PORT DATA Match to INT ↓ Delay (Mode 3)
TdPD(INT)
– – 180 ns
– – 490 ns
STROBE ↑ to INT ↓ Delay
TdSTB(INT)
– – 440 ns
Note 4 For Mode 2: tW(ST) > tS(PD)
Note 5 Increase these values by 2nsec for each 10pF increase in loading up to 100pF max.
Note 6. 2.5 TcC > (N–2) TdIEI (IEOG) + TdM1(IEO) + TsIE(IO) + TTL Buffer Delay, if any.
Pin Connection Diagram
D2 1
D7 2
D6 3
Chip Enable 4
Control Data Select 5
Port B/A Select 6
A7 7
A6 8
A5 9
A4 10
GND 11
A3 12
A2 13
A1 14
A0 15
A STB 16
B STB 17
A RDY 18
D0 19
D1 20
40 D3
39 D4
38 D5
37 M1
36 IORQ
35 RD
34 B7
33 B6
32 B5
31 B4
30 B3
29 B2
28 B1
27 B0
26 (+) 5V
25 System Clock Input
24 IEI
23 INT
22 IEO
21 B RDY
Share Link: 