NTE6664 查看數據表（PDF） - NTE Electronics

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NTE6664

Integrated Circuit 64K–Bit Dynamic RAM

NTE Electronics 

Read, Write, and Read–Modify–Write Cycles (Cont’d): (VCC = 5V ±10%, TA = 0 to +70°C

unless otherwise specified, Notes 6, 7, and 8)

Parameter

RAS to CAS Delay Time

Row Address Setup Time

Row Address Hold Time

Column Address Setup Time

Column Address Hold Time

Column Address Hold Time Referenced to RAS

Transition Time (Rise and Fall)

Read Command Setup Time

Read Command Hold Time Referenced to CAS

Read Command Hold Time Referenced to RAS

Write Command Hold Time

Write Command Hold Time Referenced to RAS

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data in Setup Time

Data in Hold Time

Data in Hold Time Referenced to RAS

CAS to RAS Precharge Time

RAS Hold Time

Refresh Period

Write Command Setup Time

CAS to Write Delay

RAS to Write Delay

CAS Hold Time

CAS Precharge Time (Page Mode Cycle Only)

Page Mode Cycle Time

RAS to REFRESH Delay

REFRESH Period (Battery Backup Mode)

REFRESH to RAS Precharge Time

(Battery Backup Mode)

REFRESH Cycle Time (Auto Pulse Mode)

REFRESH Pulse Period (Auto Period Mode)

REFRESH to RAS Setup Time (Auto Pulse Mode)

REFRESH to RAS Delay Time (Auto Pulse Mode)

REFRESH Inactive Time

RAS to REFRESH Lead Time

RAS Inactive Time During REFRESH

Symbol

tRCD

tASR

tRAH

tASC

tCAH

tAR

tT

tRCS

tRCH

tRRH

tWCH

tWCR

tWP

tRWL

tCWL

tDS

tDH

tDHR

tCRP

tRSH

tRFSH

tWCS

tCWD

tRWD

tCSH

tCP

tPC

tRFD

tFBP

tFBR

Test Conditions

Note 14

Note 18

Note 15

Note 15

Note 18

Note 16

Note 16

Note 18

Note 17

Note 17

Note 17

Min Typ

25 –

0

–

20 –

0

–

35 –

95 –

3

–

0

–

0

–

0

–

35 –

95 –

35 –

45 –

45 –

0

–

35 –

95 –

–10 –

75 –

–

–

–10 –

45 –

120 –

150 –

60 –

145 –

–10 –

2000 –

320 –

Max

75

–

–

–

–

–

50

–

–

–

–

–

–

–

–

–

–

–

–

–

2

–

–

–

–

–

–

–

–

–

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

ns

ns

ns

ns

ns

ns

ns

ns

ns

tFC

tFP

tFSR

tFRD

tFI

tFRL

tFRI

270 –

–

ns

60 – 2000 ns

–30 –

–

ns

320 –

–

ns

60 –

–

ns

370 –

–

ns

370 –

–

ns

Note 6. VIH min and VIL max are reference levels for measuring timing of input signals. Transition

times are measured between VIH and VIL.

Note 7. An initial pause of 100µs is required after power–up followed by 8 RAS cycles before proper

device operation is guaranteed.

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