ORLI10G-2BM680I 查看數據表（PDF） - Lattice Semiconductor
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ORLI10G-2BM680I
Lattice Semiconductor
ORLI10G-2BM680I Datasheet PDF : 80 Pages
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
Description
FPSC Definition
FPSCs, or Field-Programmable System Chips, are devices that combine field-programmable logic with ASIC, or
mask-programmed logic, on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the
design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the
FPGA functionality is changed; all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI, PCMs,
boundary scan, etc. Columns of programmable logic are replaced on one side of the device, allowing pins from the
replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their
FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to provide a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
Series 4-based FPSCs expand this interface by providing a link between the embedded block and the multimaster
32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-
tions, including the embedded block RAMs and the microprocessor interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This
supports user-programmable options in the embedded core, in turn allowing greater flexibility. Multiple embedded
core configurations may be designed into a single device with user-programmable control over which configura-
tions are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
ispLEVER Development System
The ispLEVER development system is used to process a design from a netlist to a configured FPGA. This system
is used to map a design onto the ORCA architecture and then place and route it using ispLEVER's timing-driven
tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design
entry, synthesis, simulation, and timing analysis.
The ispLEVER development system interfaces to front-end design entry tools and provides the tools to produce a
configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow,
the design entry and the bit stream generation stage. Recent improvements in ispLEVER allow the user to provide
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