ORLI10G-2BM680I 查看數據表（PDF） - Lattice Semiconductor
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ORLI10G-2BM680I
Lattice Semiconductor
ORLI10G-2BM680I Datasheet PDF : 80 Pages
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These
modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing
data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and
out of the I/O buffers on both edges of the clock.
The new programmable I/O cell allows designers to select I/Os which meet many new communication standards,
permitting the device to hook up directly without any external interface translation. They support traditional FPGA
standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-ori-
ented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output lev-
els.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses
with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One
PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide
high connectivity with fast software routing times and high-speed system performance.
Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be
sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing are available for fast
regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can
be sourced from any I/O pin, PLLs, or the PLC logic.
The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility
translates into an improved capability to route designs at the required speeds when the I/O signals have been
locked to specific pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system
bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly
tuned networking specific phase-locked loops. These functional blocks support easy glueless system interfacing
and the capability to adjust to varying conditions in today's high-speed networking systems.
Microprocessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-bit,
16-bit, and 32-bit interfaces with optional parity to the Motorola ® PowerPC 860 bus, it can be used for configuration
and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4
embedded system bus at 66 MHz performance.
The MPI provides, following configuration, a system-level microprocessor interface through the system bus to the
user-defined logic within the FPGA, and includes access to the embedded block RAM. The MPI supports burst
data read and write transfers, allowing short, uneven transmission of data through the interface by including data
FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-
beat (16 x 1 bytes).
The 32-bit device identification code (device_id) for the ORLI10G is at system bus register address 0x0-0x3. (see
Figure 1.)
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