ORLI10G-2BM680I 查看數據表（PDF） - Lattice Semiconductor

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ORLI10G-2BM680I

Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC

Lattice Semiconductor 

Lattice Semiconductor

ORCA ORLI10G Data Sheet

Figure 1. ORLI10G 32-bit Device Identification Code

0000_000101000_1_001000_00000011101_1

First OR4E04

based FPSC

40 rows (OR4E04)

FPSC identifier

Series 4

Manufacturer ID

System Bus

An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration

logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specifi-

cation Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements.

The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset func-

tions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is

integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the micro-

processor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from

routing, or port clock (for JTAG configuration modes). In the ORLI10G FPSC, the system bus is not connected to

the embedded core.

Phase-Locked Loops

Four user PLLs are provided for ORCA Series 4 FPSCs. Programmable PLLs can be used to manipulate the fre-

quency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks

from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x (the input clock frequency). Each program-

mable PLL provides two outputs that have different multiplication factors but can have the same phase relation-

ships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input

buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have pro-

grammable (12.5% steps) phase differences.

Additional highly tuned and characterized Dedicated Phase-Locked Loops (DPLLs) are included to ease system

designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to very

tightly target specified clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are tar-

geted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 sys-

tems.

Embedded Block RAM

New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to significantly increase the amount of mem-

ory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two

byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available,

as well as direct connection to the high-speed system bus.

Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable

multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k, including asyn-

chronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple

of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-

bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit

CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can

also be preloaded at device configuration time.

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