ORT8850L-3BM680 查看數據表（PDF） - Agere -> LSI Corporation

零件编号

产品描述 (功能)

生产厂家

ORT8850L-3BM680

ORCA® ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Agere -> LSI Corporation 

ORCA ORT8850 FPSC

Eight-Channel x 850 Mbits/s Backplane Transceiver

Data Sheet

August 2001

System-Level Features

The Series 4 also provides system-level functionality

by means of its microprocessor interface, embedded

system bus, quad-port embedded block RAMs, univer-

sal programmable phase-locked loops, and the addi-

tion of highly tuned networking specific phase-locked

loops. These functional blocks allow for easy glueless

system interfacing and the capability to adjust to vary-

ing conditions in today’s high-speed networking sys-

tems.

Microprocessor Interface

The MPI provides a glueless interface between the

FPGA and PowerPC microprocessors. Programmable

in 8-, 16-, and 32-bit interfaces with optional parity to

the Motorola® PowerPC 860 bus, it can be used for

configuration and readback, as well as for FPGA con-

trol and monitoring of FPGA status. All MPI transac-

tions utilize the Series 4 embedded system bus at 66

MHz performance.

A system-level microprocessor interface to the FPGA

user-defined logic following configuration, through the

system bus, including access to the embedded block

RAM and general user-logic, is provided by the MPI.

The MPI supports burst data read and write transfers,

allowing short, uneven transmission of data through

the interface by including data FIFOs. Transfer

accesses can be single beat (1 x 4-bytes or less), 4-

beat (4 x 4-bytes), 8-beat (8 x 2-bytes), or 16-beat (16

x 1-bytes).

System Bus

An on-chip, multimaster, 8-bit system bus with 1-bit

parity facilitates communication among the MPI, con-

figuration logic, FPGA control, and status registers,

embedded block RAMs, as well as user logic. Utilizing

the AMBA specification Rev 2.0 AHB protocol, the

embedded system bus offers arbiter, decoder, master,

and slave elements. Master and slave elements are

also available for the user-logic and embedded back-

plane transceiver portion of the 8850.

The system bus control registers can provide control to

the FPGA such as signaling for reprogramming, reset

functions, and PLL programming. Status registers

monitor INIT, DONE, and system bus errors. An inter-

rupt controller is integrated to provide up to eight possi-

ble interrupt resources. Bus clock generation can be

sourced from the microprocessor interface clock, con-

figuration clock (for slave configuration modes), inter-

nal oscillator, user clock from routing, or from the port

clock (for JTAG configuration modes).

10

Phase-Locked Loops

Up to eight PLLs are provided on each Series 4 device,

with four PLLs generally provided for FPSCs. Program-

mable PLLs can be used to manipulate the frequency,

phase, and duty cycle of a clock signal. Each PPLL is

capable of manipulating and conditioning clocks from

20 MHz to 420 MHz. Frequencies can be adjusted from

1/8x to 8x, the input clock frequency. Each programma-

ble PLL provides two outputs that have different multi-

plication factors but can have the same phase

relationships. Duty cycles and phase delays can be

adjusted in 12.5% of the clock period increments. An

automatic input buffer delay compensation mode is

available for phase delay. Each PPLL provides two out-

puts that can have programmable (12.5% steps) phase

differences.

Additional highly tuned and characterized, dedicated

phase-locked loops (DPLLs) are included to ease sys-

tem designs. These DPLLs meet ITU-T G.811 primary-

clocking specifications and enable system designers to

very tightly target specified clock conditioning not tradi-

tionally available in the universal PPLLs. Initial DPLLs

are targeted to low-speed networking DS1 and E1, and

also high-speed SONET/SDH networking STS-3 and

STM-1 systems. These DPLLs are typically not

included on FPSC devices and are not found on the

ORT8850 family.

Embedded Block RAM

New 512 x 18 quad-port RAM blocks are embedded in

the FPGA core to significantly increase the amount of

memory and complement the distributed PFU memo-

ries. The EBRs include two write ports, two read ports,

and two byte lane enables which provide four-port

operation. Optional arbitration between the two write

ports is available, as well as direct connection to the

high-speed system bus.

Additional logic has been incorporated to allow signifi-

cant flexibility for FIFO, constant multiply, and two-vari-

able multiply functions. The user can configure FIFO

blocks with flexible depths of 512k, 256k, and 1k

including asynchronous and synchronous modes and

programmable status and error flags. Multiplier capabil-

ities allow a multiple of an 8-bit number with a 16-bit

fixed coefficient or vice versa (24-bit output), or a multi-

ply of two 8-bit numbers (16-bit output). On-the-fly

coefficient modifications are available through the sec-

ond read/write port. Two 16 x 8-bit CAMs per embed-

ded block can be implemented in single match, multiple

match, and clear modes. The EBRs can also be pre-

loaded at device configuration time.

Agere Systems Inc.

Share Link: