ORT8850L-3BM680 查看數據表（PDF） - Agere -> LSI Corporation

零件编号

产品描述 (功能)

生产厂家

ORT8850L-3BM680

ORCA® ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Agere -> LSI Corporation 

Data Sheet

August 2001

ORCA ORT8850 FPSC

Eight-Channel x 850 Mbits/s Backplane Transceiver

System-Level Features (continued)

Configuration

The FPGAs functionality is determined by internal con-

figuration RAM. The FPGAs internal initialization/con-

figuration circuitry loads the configuration data at

powerup or under system control. The configuration

data can reside externally in an EEPROM or any other

storage media. Serial EEPROMs provide a simple, low

pin-count method for configuring FPGAs.

The RAM is loaded by using one of several configura-

tion modes. Supporting the traditional master/slave

serial, master/slave parallel, and asynchronous periph-

eral modes, the Series 4 also utilizes its microproces-

sor interface and embedded system bus to perform

both programming and readback. Daisy chaining of

multiple devices and partial reconfiguration are also

permitted.

Other configuration options include the initialization of

the embedded-block RAM memories and FPSC mem-

ory as well as system bus options and bit stream error

checking. Programming and readback through the

JTAG (IEEE 1149.2) port is also available meeting in-

system programming (ISP) standards (IEEE 1532

Draft).

Additional Information

Contact your local Agere representative for additional

information regarding the ORCA Series 4 FPGA

devices, or visit our website at:

http://www.agere.com/orca

Agere Systems Inc.

11

Share Link: