ORT8850L-3BM680 查看數據表（PDF） - Agere -> LSI Corporation

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ORT8850L-3BM680

ORCA® ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Agere -> LSI Corporation 

ORCA ORT8850 FPSC

Eight-Channel x 850 Mbits/s Backplane Transceiver

Data Sheet

August 2001

Embedded Core Features (Serial)

s Implemented in an ORCA Series 4 FPGA.

s Allows wide range of applications for SONET net-

work termination application as well as generic data

moving for high-speed backplane data transfer.

s No knowledge of SONET/SDH needed in generic

applications. Simply supply data, 78 MHz—106 MHz

clock, and a frame pulse.

s High-speed interface (HSI) function for clock/data

recovery serial backplane data transfer without exter-

nal clocks.

s Eight-channel HSI function provides 850 Mbits/s

serial interface per channel for a total chip bandwidth

of 6.8 Gbits/s (full duplex).

s HSI function uses Agere’s 850 Mbits/s serial inter-

face core. Rates from 212 Mbits/s to 850 Mbits/s are

supported directly (lower rates directly supported

through decimation and interpolation).

s LVDS I/Os compliant with EIA®-644 support hot

insertion. All embedded LVDS I/Os include both input

and output on-board termination to allow long-haul

driving of backplanes.

s Low-power 1.5 V HSI core.

s Low-power LVDS buffers.

s Programmable STS-1, STS-3, and STS-12 framing.

s Independent STS-1, STS-3, and STS-12 data

streams per quad channels.

s 8:1 data multiplexing/demultiplexing for 106.25 MHz

byte-wide data processing in FPGA logic.

s On-chip, phase-lock loop (PLL) clock meets B jitter

tolerance specification of ITU-T recommendation

G.958.

s Powerdown option of HSI receiver on a per-channel

basis.

s Selectable 8B/10B coder/decoder or SONET scram-

bler/descrambler.

s HSI automatically recovers from loss-of-clock once

its reference clock returns to normal operating state.

s Frame alignment across multiple ORT8850 devices

for work/protect switching at OC-192/STM-64 and

above rates.

s In-band management and configuration through

transport overhead extraction/insertion.

s Supports transparent modes where either the only

insertion is A1/A2 framing bytes, or no bytes are

inserted.

s Streamlined pointer processor (pointer mover) for

8 kHz frame alignment to system clocks.

s Built-in boundry scan (IEEE ®1149.1 JTAG).

s FIFOs align incoming data across all eight channels

(two groups of four channels or four groups of two

channels) for both SONET scrambling and 8B/10B

modes. Optional ability to bypass alignment FIFOs.

s 1 + 1 protection supports STS-12/STS-48 redun-

dancy by either software or hardware control for pro-

tection switching applications. STS-192 and above

rates are supported through multiple devices.

s ORCA FPGA soft intellectual property core support

for a variety of applications.

s Programmable STM pointer mover bypass mode.

s Programmable STM framer bypass mode.

s Programmable CDR bypass mode (clocked LVDS

high-speed interface).

s Redundant outputs and multiplexed redundant inputs

for CDR I/Os allow for implementation of eight chan-

nels with redundancy on a single device.

Embedded Core Features (Parallel)

s Three full-duplex, double data rate (DDR) I/O groups

include 8-bit data, one control, and one clock. Each

interface is implemented with LVDS I/Os that include

on-board termination to allow long-haul driving of

backplanes, such as the industry-standard RapidIO

interface.

s External I/O speeds on DDR interface up to

311 MHz (622 Mbits/s per pin), with internal, single-

edge data transferred at 1/2 rate on a 32-bit bus plus

control.

s Automatic centering of transmit clock in data eye for

DDR interface.

s Direct interfaces to Agere Pi-Sched (266 MHz DDR

LVDS), Pi-X (128 MHz TTL), and APC (100 MHz

TTL) ATM/IP switch/port controller devices.

4

Agere Systems Inc.

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