ORT8850L-3BM680 查看數據表（PDF） - Agere -> LSI Corporation

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ORT8850L-3BM680

ORCA® ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Agere -> LSI Corporation 

Data Sheet

August 2001

ORCA ORT8850 FPSC

Eight-Channel x 850 Mbits/s Backplane Transceiver

Programmable FPGA Features

s High-performance platform design:

— 0.13 µm 7-level metal technology.

— Internal performance of >250 MHz.

— Over 600K usable system gates.

— Meets multiple I/O interface standards.

— 1.5 V operation (30% less power than 1.8 V oper-

ation) translates to greater performance.

s Traditional I/O selections:

— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/

Os.

— Per pin-selectable I/O clamping diodes provide

3.3 V PCI compliance.

— Individually programmable drive capability:

24 mA sink/12 mA source, 12 mA sink/6 mA

source, or 6 mA sink/3 mA source.

— Two slew rates supported (fast and slew-limited).

— Fast-capture input latch and input flip-flop

(FF)/latch for reduced input setup time and zero

hold time.

— Fast open-drain drive capability.

— Capability to register 3-state enable signal.

— Off-chip clock drive capability.

— Two-input function generator in output path.

s New programmable high-speed I/O:

— Single-ended: GTL, GTL+, PECL, SSTL3/2

(class I & II), HSTL (Class I, III, IV), ZBT, and

DDR.

— Double-ended: LVDS, bused-LVDS, LVPECL.

— LVDS include optional on-chip termination resistor

per I/O and on-chip reference generation.

— Customer defined: ability to substitute arbitrary

standard-cell I/O to meet fast-moving standards.

s New capability to (de)multiplex I/O signals:

— New DDR on both input and output at rates up to

133 MHz (266 MHz effective rate).

— New 2x and 4x downlink and uplink capability per

I/O (i.e., 50 MHz internal to 200 MHz I/O).

s Enhanced twin-quad programmable function unit

(PFU):

— Eight 16-bit look-up tables (LUTs) per PFU.

— Nine user registers per PFU, one following each

LUT, and organized to allow two nibbles to act

independently, plus one extra for arithmetic opera-

tions.

— New register control in each PFU has two inde-

pendent programmable clocks, clock enables,

local set/reset, and data selects.

— New LUT structure allows flexible combinations of

LUT4, LUT5, new LUT6, 4 → 1 MUX, new

8 → 1 MUX, and ripple mode arithmetic functions

in the same PFU.

— 32 x 4 RAM per PFU, configurable as single- or

Agere Systems Inc.

dual-port. Create large, fast RAM/ROM blocks

(128 x 8 in only eight PFUs) using the SLIC

decoders as bank drivers.

— Soft-wired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU

through fast internal routing, which reduces rout-

ing congestion and improves speed.

— Flexible fast access to PFU inputs from routing.

— Fast-carry logic and routing to all four adjacent

PFUs for nibble-wide, byte-wide, or longer arith-

metic functions, with the option to register the PFU

carry-out.

s Abundant high-speed buffered and nonbuffered rout-

ing resources provide 2x average speed improve-

ments over previous architectures.

s Hierarchical routing optimized for both local and glo-

bal routing with dedicated routing resources. This

results in faster routing times with predictable and

efficient performance.

s SLIC provides eight 3-statable buffers, up to 10-bit

decoder, and PAL®-like and-or-invert (AOI) in each

programmable logic cell.

s Improved built-in clock management with dual-output

programmable phase-locked loops (PPLLs) provide

optimum clock modification and conditioning for

phase, frequency, and duty cycle from 20 MHz up to

416 MHz.

s New 200 MHz embedded quad-port RAM blocks,

two read ports, two write ports, and two sets of byte

lane enables. Each embedded RAM block can be

configured as:

— One—512 x 18 (quad-port, two read/two write)

with optional built-in arbitration.

— One—256 x 36 (dual-port, one read/one write).

— One—1K x 9 (dual-port, one read/one write).

— Two—512 x 9 (dual-port, one read/one write for

each).

— Two RAM with arbitrary number of words whose

sum is 512 or less by 18 (dual-port, one read/one

write).

— Supports joining of RAM blocks.

— Two 16 x 8-bit content addressable memory

(CAM) support.

— FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.

— Constant multiply (8 x 16 or 16 x 8).

— Dual variable multiply (8 x 8).

s Embedded 32-bit internal system bus plus 4-bit par-

ity interconnects FPGA logic, microprocessor inter-

face (MPI), embedded RAM blocks, and embedded

backplane transceiver blocks with 100 MHz bus per-

formance. Included are built-in system registers that

act as the control and status center for the device.

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