ORT42G5-1BM484C 查看數據表（PDF） - Lattice Semiconductor
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ORT42G5-1BM484C Datasheet PDF : 119 Pages
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Table of Contents
Introduction .................................................................. 1
Table of Contents......................................................... 2
Embedded Function Features...................................... 4
Programmable Features .............................................. 5
Programmable Logic System Features........................ 6
Description ................................................................... 7
What is an FPSC?........................................... 7
FPSC Overview............................................... 7
FPSC Gate Counting ...................................... 7
FPGA/Embedded Core Interface .................... 7
FPSC Design Kit ............................................. 7
FPGA Logic Overview..................................... 8
PLC Logic........................................................ 8
Programmable I/O........................................... 8
Routing............................................................ 9
System-Level Features ................................................ 9
Microprocessor Interface................................. 9
System Bus ................................................... 10
Phase-Locked Loops .................................... 10
Embedded Block RAM .................................. 10
Configuration................................................. 10
Additional Information ................................... 11
ORT42G5/ORT82G5 Overview ................................. 11
Embedded Core Overview ............................ 11
Serializer and Deserializer (SERDES) .......... 11
MUX/DEMUX Block ...................................... 12
Multi-channel Alignment FIFOs..................... 12
XAUI and Fibre Channel Link State
Machines....................................................... 12
FPGA/Embedded Core Interface .................. 12
Dual Port RAMs ............................................ 13
FPSC Configuration ...................................... 13
Backplane Transceiver Core Detailed Description .... 13
8b/10b Encoding and Decoding .................... 14
Transmit Path (FPGA to Backplane) Logic ... 16
8b/10b Encoder and 1:10 Multiplexer ........... 18
CML Output Buffer ........................................ 18
Receive Path (Backplane to FPGA) Logic .... 19
Link State Machines...................................... 24
XAUI Link Synchronization Function............. 25
Multi-channel Alignment............................................. 27
ORT42G5 Multi-channel Alignment .............. 27
ORT82G5 Multi-channel Alignment .............. 28
XAUI Lane Alignment Function
(Lane Deskew) ....................................... 29
Mixing Half-rate, Full-rate Modes .................. 30
Multi-channel Alignment Configuration ...................... 30
ORT42G5 Configuration ............................... 30
ORT82G5 Configuration ............................... 31
ORT42G5 Alignment Sequence.................... 32
ORT82G5 Alignment Sequence.................... 33
Reference Clocks and Internal Clock Distribution...... 37
Reference Clock Requirements .................... 37
Synthesized and Recovered Clocks ............. 37
Internal Clock Signals at the FPGA/Core Interface
for the ORT42G5 ................................................. 38
Transmit and Receive Clock Rates............... 39
Transmit Clock Source Selection .................. 39
Recommended Transmit Clock Distribution
for the ORT42G5 .................................... 39
Multi-Channel Alignment Clocking
Strategies for the ORT42G5 ................... 41
Internal Clock Signals at the FPGA/Core Interface
for the ORT82G5 ................................................. 43
Transmit and Receive Clock Rates............... 44
Transmit Clock Source Selection .................. 44
Recommended Transmit Clock Distribution
for the ORT82G5 .................................... 45
Multi-Channel Alignment Clocking
Strategies for the ORT82G5 ................... 47
Reset Operation ......................................................... 49
Start Up Sequence for the ORT42G5 ........... 50
Start Up Sequence for the ORT82G5 ........... 51
Test Modes ................................................................ 52
Loopback Testing.......................................... 52
High-Speed Serial Loopback at the CML
Buffer Interface ....................................... 53
Parallel Loopback at the SERDES
Boundary ................................................ 54
Parallel Loopback at MUX/DEMUX
Boundary, Excluding SERDES ............... 55
SERDES Characterization Test Mode
(ORT82G5 Only)..................................... 55
Embedded Core Block RAM ...................................... 56
Memory Maps ............................................................ 59
Definition of Register Types .......................... 59
ORT42G5 Memory Map................................ 59
ORT82G5 Memory Map................................ 67
Recommended Board-level Clocking for
the ORT42G5 and ORT82G5 ................. 73
Absolute Maximum Ratings ....................................... 75
Recommended Operating Conditions ........................ 75
SERDES Electrical and Timing Characteristics ......... 75
High Speed Data Transmitter........................ 76
High Speed Data Receiver............................ 77
External Reference Clock ............................. 79
Embedded Core Timing Characteristics ....... 79
Pin Descriptions ......................................................... 80
Power Supplies for ORT42G5 AND ORT82G5.......... 85
Power Supply Descriptions ........................... 85
Recommended Power Supply
Connections............................................ 85
Recommended Power Supply Filtering
Scheme................................................... 85
Package Information .................................................. 87
Package Pinouts ........................................... 87
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