ORT42G5-3BM680C 查看數據表（PDF） - Lattice Semiconductor

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ORT42G5-3BM680C

0.6 to 3.7 Gbps XAUI and FC FPSCs

Lattice Semiconductor 

Lattice Semiconductor

ORCA ORT42G5 and ORT82G5 Data Sheet

– 1—512 x 18 (block-port, two read/two write) with optional built in arbitration.

– 1—256 x 36 (dual-port, one read/one write).

– 1—1K x 9 (dual-port, one read/one write).

– 2—512 x 9 (dual-port, one read/one write for each).

– 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).

– Supports joining of RAM blocks.

– Two 16 x 8-bit content addressable memory (CAM) support.

– FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.

– Constant multiply (8 x 16 or 16 x 8).

– Dual variable multiply (8 x 8).

• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI),

embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-

in system registers that act as the control and status center for the device.

• Built-in testability:

– Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG).

– Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7.

– TS_ALL testability function to 3-state all I/O pins.

– New temperature-sensing diode.

• Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock

modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of

the input frequency up to 64x and division of the input frequency down to 1/64x possible.

• New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route.

This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide

reduced ground bounce for output buses by allowing flexible delays of switching output buffers.

• Per channel Pseudo-Random Bit Sequence (PRBS) generator and checker in FPGA logic.

Programmable Logic System Features

• PCI local bus compliant for FPGA I/Os.

• Improved PowerPC ® 860 and PowerPC II high-speed synchronous microprocessor interface can be used for

configuration, readback, device control, and device status, as well as for a general-purpose interface to the

FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors

with user-configurable address space provided.

• New embedded system bus facilitates communication among the microprocessor interface, configuration logic,

Embedded Block RAM, FPGA logic, and embedded standard cell blocks.

• Variable size bused readback of configuration data capability with the built-in microprocessor interface and sys-

tem bus.

• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.

• New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200

ps for OR4E04).

• New local clock routing structures allow creation of localized clock trees.

• Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved

setup/hold and clock to out performance.

• New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-

speed memory interfaces.

• New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal

logic.

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