M35080 查看數據表（PDF） - STMicroelectronics
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M35080 Datasheet PDF : 18 Pages
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M35080
Figure 4. EEPROM and SPI Bus
SPI Interface with D
(CPOL, CPHA) = Q
('0', '0') or ('1', '1')
C
Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
CQD
M35xxx
S
CQD
M35xxx
S
CQD
M35xxx
S
AI02148C
OPERATIONS
All instructions, addresses and data are shifted se-
rially in and out of the chip (along the bus, as
shown in Figure 4). The most significant bit is pre-
sented first, with the data input (D) sampled on the
first rising edge of the clock (C) after the chip se-
lect (S) goes low (as shown in Figure 5, Figure 9,
and Figure 12).
Every instruction, as summarized in Table 5, starts
with a single-byte code. If an invalid instruction is
sent (one not contained in Table 5), the chip auto-
matically deselects itself.
The instruction code is entered via the data input
(D), and latched on the rising edge of the clock in-
put (C). To enter an instruction code, the device
must have been previously selected (S held low).
Protection of the First 32 Bytes
The first 32-byte page is organized as 16 words
(two bytes each). The initial content of each word
on this page is 0000h. When writing to byte-pair, a
logic comparator verifies that the new two-byte
value is larger than the value currently stored. If
the new value is smaller than the current one, no
operation is performed. It is impossible to write a
value lower than the previous one, irrespective of
the state of W pin and status register, as indicated
in Table 6.
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR oper-
ation. The WREN instruction (write enable) sets
this latch, and the WRDI instruction (write disable)
resets it.
Table 5. Instruction Set
Instruction
Description
WREN
Set Write Enable Latch
WRDI
Reset Write Enable Latch
RDSR
Read Status Register
WRSR
Write Status Register
READ
Read Data from Memory Array
WRITE
Write Data to Memory Array
WRINC
Write Data to Secure Array
4/18
Instruction Format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
0000 0111
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