PIC16LC72-02I/JW 查看數據表（PDF） - Microchip Technology
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PIC16LC72-02I/JW Datasheet PDF : 124 Pages
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PIC16C72 Series
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1* RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)
* Maintain this bit clear to ensure upward com-
patibility with future products.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM.
All implemented banks contain special function regis-
ters. Some “high use” special function registers from
one bank may be mirrored in another bank for code
reduction and quicker access (ex; the STATUS register
is in Bank 0 and Bank 1).
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indi-
rectly through the File Select Register FSR
(Section 2.5).
FIGURE 2-2: REGISTER FILE MAP
File
Address
00h INDF(1)
01h TMR0
02h
PCL
03h STATUS
04h
FSR
05h PORTA
06h PORTB
07h PORTC
08h
09h
0Ah PCLATH
0Bh INTCON
0Ch PIR1
0Dh
0Eh TMR1L
0Fh TMR1H
10h T1CON
11h TMR2
12h T2CON
13h SSPBUF
14h SSPCON
15h CCPR1L
16h CCPR1H
17h CCP1CON
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh ADRES
1Fh ADCON0
20h
General
Purpose
Register
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
General
Purpose
Register
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
7Fh
Bank 0
FFh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS39016A-page 6
Preliminary
© 1998 Microchip Technology Inc.
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