PIC16LC72T-02I/SS 查看數據表（PDF） - Microchip Technology

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PIC16LC72T-02I/SS

8-Bit CMOS microcontroller with A,D converter

Microchip Technology 

PIC16C72 Series

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The special function registers can be classified into two

sets (core and peripheral). Those registers associated

with the “core” functions are described in this section,

and those related to the operation of the peripheral fea-

tures are described in the section of that peripheral fea-

ture.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(3)

Bank 0

00h(1) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx uuuu uuuu

02h(1) PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

03h(1) STATUS

IRP(4)

RP1(4)

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

04h(1) FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h

PORTA

—

— PORTA Data Latch when written: PORTA pins when read

--0x 0000 --0u 0000

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

08h

—

Unimplemented

—

—

09h

0Ah(1,2)

0Bh(1)

—

PCLATH

INTCON

Unimplemented

—

—

GIE

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

—

—

---0 0000 ---0 0000

0000 000x 0000 000u

0Ch

PIR1

—

ADIF

—

—

SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

0Dh

—

Unimplemented

—

—

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000 0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h

SSPCON

WCOL SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h

CCPR1L

Capture/Compare/PWM Register (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

—

CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h-1Dh

—

Unimplemented

—

—

1Eh

ADRES

A/D Result Register

xxxx xxxx uuuu uuuu

1Fh

ADCON0

ADCS1 ADCS0 CHS2

CHS1

CHS0 GO/DONE

—

ADON 0000 00-0 0000 00-0

Legend:

Note 1:

2:

3:

4:

5:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from either bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.

SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.

© 1998 Microchip Technology Inc.

Preliminary

DS39016A-page 7

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