PIC16C72-02E 查看數據表（PDF） - Microchip Technology

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PIC16C72-02E

8-Bit CMOS microcontroller with A,D converter

Microchip Technology 

PIC16C72 Series

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(3)

Bank 1

80h(1) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h

OPTION_REG RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111 1111 1111

82h(1) PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

83h(1) STATUS

IRP(4)

RP1(4)

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

84h(1) FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

85h

TRISA

—

— PORTA Data Direction Register

--11 1111 --11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

87h

TRISC

PORTC Data Direction Register

1111 1111 1111 1111

88h

—

Unimplemented

—

—

89h

8Ah(1,2)

8Bh(1)

—

PCLATH

INTCON

Unimplemented

—

—

GIE

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the PC

INTE

RBIE

T0IF

INTF

RBIF

—

—

---0 0000 ---0 0000

0000 000x 0000 000u

8Ch

PIE1

—

ADIE

—

—

SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

8Dh

—

Unimplemented

—

—

8Eh

PCON

—

—

—

—

—

—

POR

BOR ---- --qq ---- --uu

8Fh

—

Unimplemented

—

—

90h

—

Unimplemented

—

—

91h

—

Unimplemented

—

—

92h

PR2

Timer2 Period Register

93h

SSPADD

Synchronous Serial Port (I2C mode) Address Register

94h

SSPSTAT

SMP(5)

CKE(5)

D/A

P

S

R/W

UA

1111 1111 1111 1111

0000 0000 0000 0000

BF 0000 0000 0000 0000

95h

—

Unimplemented

—

—

96h

—

Unimplemented

—

—

97h

—

Unimplemented

—

—

98h

—

Unimplemented

—

—

99h

—

Unimplemented

—

—

9Ah

—

Unimplemented

—

—

9Bh

—

Unimplemented

—

—

9Ch

—

Unimplemented

—

—

9Dh

—

Unimplemented

—

—

9Eh

—

Unimplemented

—

—

9Fh

ADCON1

—

—

—

—

—

PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend:

Note 1:

2:

3:

4:

5:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from either bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.

SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.

DS39016A-page 8

Preliminary

© 1998 Microchip Technology Inc.

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