PCA9504A 查看數據表（PDF） - Philips Electronics
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PCA9504A Datasheet PDF : 29 Pages
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Philips Semiconductors
Glue chip 4
Product data
PCA9504A
PIN DESCRIPTION
PIN(S)
1
3I
2
P
3
P
4
3IU
5
REF
6
REF
7
5V OD
8
5V OD
9
3I
10
3IU
11, 29, 43 G
12
3I
13
3O
14
3IU
15
3O
16
5O
17
3IOD
18
5IOD
19
3IOD
20
5IOD
21
3IU
22
3I
23
5V OD
24
5V OD
25
5IU
26
5IU
27
5IU
28
5V OD
30
5O
31
5V OD
32
5IU
33
5IU
34
3O
35
5V OD
36
3I
37
3IU
38
3IU
39
5V OD
40
5V OD
41
5ID
42
3O
44
AO
45
5I
46
3IU
47
5O
48
AO
49
3I
2004 May 11
SYMBOL
VREF3IN
V_5P0_STBY
V_3P3_STBY
GPO_FLUSH_CACHE / GP2_IN
A20M / GP1_INB
INIT / GP1_INA
FLUSH_OUT_CPU / GP1_OUT
INIT_OUT / GP2_OUT
CLK_IN
SEL_33_66
GND
PCRIST
PCRIST_OUT
AUD_EN
AUD_RST
IDE_RSTDRV
3V_DDCSCL
5V_DDCSCL
3V_DDCSDA
5V_DDCSDA
CPU_PRESENT
SLP_S3
PS_ON
HD_LED
PRIMARY_HD
SCSI
SECONDARY_HD
BACKFEED_CUT
LATCHED_BACKFEED_CUT
FLUSH_OUT_FWH
PWRGD_PS
FPRST
PWRGD_3V
SCK_BJT_GATE
SLP_S5
GRN_BLNK
YLW_BLNK
YLW_LED
GRN_LED
TEST_EN
RSMRST
REF5V
VREF5IN
MUTE_AUD
AUD_SHDN
REF5V_STBY
HSYNC_3V
FUNCTION
3.3 V input
5 V system standby power supply
3 V system standby power supply
GPO from SIO / ICH2 / Buffer 2 input
A20M signal from ICH2 / NAND 1 input B
INIT signal from the ICH2 / Buffer 1 input A
Open drain signal, goes to the CPU / NAND 1 output
Delayed INIT signal into the CPU / Buffer 2 output
Either 33MHz or 66MHz clock, based on SEL_33_66 pin
Strapping option for 33MHz or 66MHz CLK_IN
Ground
PCI reset signal
Copy of PCRIST, increased drive-strength
Audio enable input (GPO from ICH2 / SIO)
Audio reset output
IDE reset output, 5 V push/pull
DDCSCL input/output 3.3 V side
DDCSCL input/output 5 V side
DDCSDA input/output 3.3 V side
DDCSDA input/output 5 V side
CPU present signal from the processor
Signal from ICH2 for transitioning to the S3 power state
Power supply turn-on signal
Hard drive front panel LED output
IDE primary drive active input
SCSI drive active input
IDE secondary drive active input
Signal used for STR circuitry
Signal used for STR circuitry
Open drain signal, goes to the FWH
Power good signal from power supply
Reset signal from the front panel
3.3 V power good output
Gate signal from the SCK BJT in suspend to RAM
Signal from the ICH2 for transitioning to the S5 power state
Power LED input, from SIO GPIO
Power LED input, from SIO GPIO
Power LED output
Power LED output
Test enable, 100K internal pull-down to GND
Reset for the ICH2 resume well
Highest system supply reference voltage
5V system primary supply input
Signal from SIO to mute audio on power up/down
Signal to audio amp to signal shutdown
Highest system standby voltage
HSYNCH input from chipset video
3
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