NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
data from
shift register
write configuration
pulse
I/O configuration
register
DQ
CK Q
data from
shift register
DQ
write pulse
CK
output port
register
read pulse
configuration port register data (Cx[y])
output port register data (Ox[y])
input port
register
D
Q
CK
100 kΩ
VDD
PCA9505
only
IOx_y
ESD protection
diode
VSS
Mx[y]
INTERRUPT
MANAGEMENT INT
input port
register data
(Ix[y])
data from
shift register
polarity inversion
register
D
Q
write polarity
pulse
CK
On power-up or RESET, all registers return to default values.
Fig 2. Simplified schematic of IO0_0 to IO4_7
polarity
register data
(Px[y])
002aab493
PCA9505_9506_3
Product data sheet
Rev. 03 — 6 June 2007
© NXP B.V. 2007. All rights reserved.
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