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PCA9508 Datasheet PDF : 21 Pages
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NXP Semiconductors
PCA9508
Hot swappable level translating I2C-bus repeater
On the B bus side of the PCA9508, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9508. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9508 for a short delay while the A bus side rises above 0.5VCC(A) then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9508 (VIL) be at or below 0.4 V to be
recognized by the PCA9508 and then transmitted to the A bus side.
Multiple PCA9508 A sides can be connected in a star configuration (Figure 5), allowing all
nodes to communicate with each other.
Multiple PCA9508s can be connected in series (Figure 6) as long as the A side is
connected to the B side. I2C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
SDA
SCL
BUS
MASTER
VCC(A)
VCC(B)
10 kΩ
10 kΩ
VCC(A)
SDAA
SCLA
10 kΩ
VCC(B)
SDAB
SCLB
PCA9508
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
VCC(A)
SDAA
SCLA
10 kΩ
VCC(B)
SDAB
SCLB
PCA9508
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
Fig 5. Typical star application
VCC(A)
SDAA
SCLA
10 kΩ
VCC(B)
SDAB
SCLB
PCA9508
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
002aac655
PCA9508_1
Product data sheet
Rev. 01 — 28 April 2008
© NXP B.V. 2008. All rights reserved.
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