PCA8536 查看數據表（PDF） - NXP Semiconductors.

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PCA8536

Automotive LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

NXP Semiconductors

PCA8536

Automotive LCD low multiplex driver with 6 channel PWM generator

BP0 12

BP1 13

BP2 14

BP3 15

BP4/S43 16

BP5/S42 17

BP6/S41 18

BP7/S40 19

S20 20

S21 21

S22 22

S23 23

S24 24

S25 25

S26 26

S27 27

S28 28

39 S39

38 S38

37 S37

36 S36

35 S35

34 S34

33 S33

32 S32

31 S31

30 S30

29 S29

S32 12

S33 13

S34 14

S35 15

S36 16

S37 17

S38 18

S39 19

S20 20

S21 21

S22 22

S23 23

S24 24

S25 25

S26 26

S27 27

S28 28

39 BP0

38 BP1

37 BP2

36 BP3

35 BP4/S43

34 BP5/S42

33 BP6/S41

32 BP7/S40

31 S31

30 S30

29 S29

BPS = 0

Fig 5. Effect of backplane swapping

BPS = 1

013aaa432

8.1.4.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)

The DC offset of the voltage across the LCD is compensated over a certain period:

line-wise in line inversion mode (driving scheme A) or frame-wise in frame inversion mode

(driving scheme B). With the INV bit (see Table 8), the compensation mode can be

switched.

In frame inversion mode, the DC value is compensated across two frames and not within

one frame. Changing the inversion mode to frame inversion reduces the power

consumption; therefore it is useful when power consumption is a key point in the

application.

Frame inversion may not be suitable for all applications. The RMS voltage across a

segment is better defined; however, since the switching frequency is reduced, there is

possibility for flicker to occur.

The waveforms of Figure 15 on page 29 to Figure 18 on page 32 are showing line

inversion mode. Figure 19 on page 33 shows an example of frame inversion.

8.1.4.3 Power-down mode

The power-down bit (PD) allows the PCA8536 to be put in a minimum power

configuration. In order to avoid display artefacts, it is recommended to enter power-down

only after the display has been switched off by setting bit E to logic 0.

During power-down, the internal oscillator is switched off and any selected PWM output is

revert to the static value stored in bits GPO0 to GPO5. These bits may be programmed to

give a static logic 0 or static logic 1 on selected GP0 to GP5 pins.

PCA8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 21 February 2012

© NXP B.V. 2012. All rights reserved.

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