PCA9530DP 查看數據表（PDF） - NXP Semiconductors.

零件编号

产品描述 (功能)

生产厂家

PCA9530DP

2-bit I2C-bus LED dimmer

NXP Semiconductors. 

NXP Semiconductors

PCA9530

2-bit I2C-bus LED dimmer

6.3.5 PWM1 - Pulse Width Modulation 1

The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED on)

when the count is less than the value in PWM1 and HIGH (LED off) when it is greater.

If PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off).

The duty cycle of BLINK1 = PWM1 / 256.

Table 8.

Bit

Symbol

Default

PWM1 - Pulse Width Modulation 1 register description

7

6

5

4

3

2

PWM1 PWM1 PWM1 PWM1 PWM1 PWM1

[7]

[6]

[5]

[4]

[3]

[2]

1

0

0

0

0

0

1

PWM1

[1]

0

0

PWM1

[0]

0

6.3.6 LS0 - LED selector

The LS0 LED select register determines the source of the LED data.

00 = output is set high-impedance (LED off; default)

01 = output is set LOW (LED on)

10 = output blinks at PWM0 rate

11 = output blinks at PWM1 rate

Table 9. LS0 - LED selector register bit description

Legend: * default value.

Register Bit

Value

Description

LS0

7:4

1111*

reserved

3:2

00*

LED1 selected

1:0

00*

LED0 selected

6.4 Pins used as GPIOs

LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs).

For use as input, set LEDn to high-impedance (00) and then read the pin state via the

INPUT register.

For use as output, connect external pull-up resistor to the pin and size it according to the

DC recommended operating characteristics. LEDn output pin is HIGH when the output is

programmed as high-impedance, and LOW when the output is programmed LOW through

the ‘LED selector’ register LS0. The output can be pulse-width controlled when PWM0 or

PWM1 are used.

6.5 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9530 in

a reset condition until VDD has reached VPOR. At that point, the reset condition is released

and the PCA9530 registers are initialized to their default states, all the outputs in the

OFF state. Thereafter, VDD must be lowered below 0.2 V to reset the device.

PCA9530_3

Product data sheet

Rev. 03 — 26 February 2009

© NXP B.V. 2009. All rights reserved.

6 of 24

Share Link: