PCA9535A 查看數據表（PDF） - NXP Semiconductors.
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PCA9535A Datasheet PDF : 38 Pages
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NXP Semiconductors
PCA9535A
Low-voltage 16-bit I2C-bus I/O port with interrupt
6. Functional description
Refer to Figure 1 “Block diagram of PCA9535A”.
6.1 Device address
slave address
0 1 0 0 A2 A1 A0 R/W
fixed
hardware
selectable
002aah371
Fig 4. PCA9535A device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9535A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7 B6 B5 B4 B3 B2 B1 B0
002aaf540
Fig 5. Pointer register bits
Table 4. Command byte
Pointer register bits
Command byte Register
B7 B6 B5 B4 B3 B2 B1 B0 (hexadecimal)
00000000
00h
Input port 0
00000001
01h
Input port 1
00000010
02h
Output port 0
00000011
03h
Output port 1
00000100
04h
Polarity Inversion port 0
00000101
05h
Polarity Inversion port 1
00000110
06h
Configuration port 0
00000111
07h
Configuration port 1
[1] Undefined.
Protocol
Power-up
default
read byte
read byte
read/write byte
read/write byte
read/write byte
read/write byte
read/write byte
read/write byte
xxxx xxxx[1]
xxxx xxxx
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
1111 1111
PCA9535A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 September 2012
© NXP B.V. 2012. All rights reserved.
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