PCA9536 查看數據表（PDF） - NXP Semiconductors.

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PCA9536

4-bit I2C-bus and SMBus I/O port

NXP Semiconductors. 

NXP Semiconductors

PCA9536

4-bit I2C-bus and SMBus I/O port

6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output. At reset, the

I/Os are configured as inputs with a weak pull-up to VDD.

‘Not used’ bits can be programmed with either logic 0 or logic 1.

Table 8. Register 3 - Configuration register bit description

Legend: * default value

Bit Symbol Access Value

Description

7

C7

R/W

1*

not used

6

C6

R/W

1*

5

C5

R/W

1*

4

C4

R/W

1*

3

C3

R/W

1*

configures the directions of the I/O pins

2

C2

1

C1

0

C0

R/W

1*

R/W

1*

R/W

1*

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input

(default value)

6.2 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in

a reset condition until VDD has reached VPOR. At that point, the reset condition is released

and the PCA9536 registers and state machine will initialize to their default states.

Thereafter, VDD must be lowered below 0.2 V to reset the device.

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the

operating voltage.

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input with a weak pull-up (100 k typical) to VDD. The input voltage may

be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the

state of the Output Port register. Care should be exercised if an external voltage is applied

to an I/O configured as an output because of the low-impedance paths that exist between

the pin and either VDD or VSS.

PCA9536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 7 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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