PCA9536 查看數據表（PDF） - NXP Semiconductors.
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PCA9536 Datasheet PDF : 24 Pages
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NXP Semiconductors
PCA9536
4-bit I2C-bus and SMBus I/O port
data from
shift register
data from
shift register
write configuration
pulse
configuration
register
D
Q
FF
CK Q
write pulse
read pulse
data from
shift register
write polarity
pulse
DQ
FF
CK
output port
register
Q1
input port
register
D
Q
FF
CK
polarity inversion
register
D
Q
FF
CK
Remark: At power-on reset, all registers return to default values.
Fig 5. Simplified schematic of IO0 to IO3
100 kΩ
Q2
output port
register data
VDD
IO0 to IO3
VSS
input port
register data
polarity inversion
register data
002aab852
6.4 Device address
slave address
1 0 0 0 0 0 1 R/W
fixed
002aab853
Fig 6. PCA9536 device address
6.5 Bus transactions
Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7
and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function, so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
PCA9536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 7 November 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
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