PCA9538ABSHP 查看數據表（PDF） - NXP Semiconductors.

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PCA9538ABSHP

Low-voltage 8-bit I2C-bus I/O port with interrupt and reset

NXP Semiconductors. 

NXP Semiconductors

PCA9538A

Low-voltage 8-bit I2C-bus I/O port with interrupt and reset

6. Functional description

Refer to Figure 1 “Block diagram of PCA9538A”.

6.1 Device address

slave address

1 1 1 0 0 A1 A0 R/W

fixed

hardware

selectable

002aae707

Fig 4. PCA9538A address

A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)

or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the

slave address (R/W) defines the operation (read or write) to be performed. A HIGH

(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.

6.2 Pointer register and command byte

Following the successful acknowledgement of the address byte, the bus master sends a

command byte, which is stored in the Pointer register in the PCA9538A. Two bits of this

data byte state the operation (read or write) and the internal registers (Input, Output,

Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower

three bits of the Command byte are used to point to the extended features of the device

(Agile I/O). This register is write only.

B7 B6 B5 B4 B3 B2 B1 B0

002aaf540

Fig 5. Pointer register bits

Table 4. Command byte

Pointer register bits

Command byte Register

B7 B6 B5 B4 B3 B2 B1 B0 (hexadecimal)

00000000

00h

Input port

00000001

01h

Output port

00000010

02h

Polarity Inversion

00000011

03h

Configuration

[1] Undefined.

Protocol

read byte

read/write byte

read/write byte

read/write byte

Power-up

default

xxxx xxxx[1]

1111 1111

0000 0000

1111 1111

PCA9538A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 28 September 2012

© NXP B.V. 2012. All rights reserved.

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