PCA9538APW 查看數據表（PDF） - NXP Semiconductors.

零件编号

产品描述 (功能)

生产厂家

PCA9538APW

Low-voltage 8-bit I2C-bus I/O port with interrupt and reset

NXP Semiconductors. 

NXP Semiconductors

PCA9538A

Low-voltage 8-bit I2C-bus I/O port with interrupt and reset

6.6 Power-on reset

When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCA9538A

in a reset condition until VDD has reached VPOR. At that time, the reset condition is

released and the PCA9538A registers and I2C-bus/SMBus state machine initialize to their

default states. After that, VDD must be lowered to below VPORF and back up to the

operating voltage for a power-reset cycle. See Section 8.3 “Power-on reset requirements”.

6.7 Reset input (RESET)

The RESET input can be asserted to initialize the system while keeping the VDD at its

operating level. A reset can be accomplished by holding the RESET pin LOW for a

minimum of tw(rst). The PCA9538A registers and I2C-bus/SMBus state machine are

changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O

levels at the P port can be changed externally or through the master. This input requires a

pull-up resistor to VDD if no active connection is used.

6.8 Interrupt output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.

After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when

data on the port is changed to the original setting or when data is read from the port that

generated the interrupt (see Figure 10). Resetting occurs in the Read mode at the

acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL

signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very

short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after

resetting is detected and is transmitted as INT.

A pin configured as an output cannot cause an interrupt. Changing an I/O from an output

to an input may cause a false interrupt to occur, if the state of the pin does not match the

contents of the Input port register.

The INT output has an open-drain structure and requires a pull-up resistor to VDD. INT

should be connected to the voltage source of the device that requires the interrupt

information. When using the input latch feature, the input pin state is latched. The interrupt

is reset only when data is read from the port that generated the interrupt. The reset occurs

in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the

rising edge of the SCL signal.

PCA9538A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 28 September 2012

© NXP B.V. 2012. All rights reserved.

8 of 37

Share Link: