PCA9538 查看數據表（PDF） - NXP Semiconductors.
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PCA9538 Datasheet PDF : 28 Pages
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NXP Semiconductors
PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactions
Data is transmitted to the PCA9538 registers using the write mode as shown in Figure 7
and Figure 8. Data is read from the PCA9538 registers using the read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 0 1 A
data to port
DATA 1
STOP
condition
AP
START condition
write to port
data out from port
R/W acknowledge
from slave
Expanded diagram is shown in Figure 18.
Fig 7. Write to output port register
acknowledge
from slave
acknowledge
from slave
tv(Q)
DATA 1 VALID
002aae708
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A
data to register
DATA 1
START condition
data to register
R/W acknowledge
from slave
acknowledge
from slave
Fig 8. Write to configuration or polarity inversion registers
STOP
condition
AP
acknowledge
from slave
002aae709
PCA9538_5
Product data sheet
Rev. 05 — 28 May 2009
© NXP B.V. 2009. All rights reserved.
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