PCA9539APW 查看數據表（PDF） - NXP Semiconductors.
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PCA9539APW Datasheet PDF : 39 Pages
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NXP Semiconductors
PCA9539A
Low voltage 16-bit I2C-bus I/O port with interrupt and reset
6.2.3 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 7.1 and a register pair read is described in Section 7.2.
Table 7.
Bit
Symbol
Default
Output port 0 register (address 02h)
7
6
5
4
O0.7
O0.6
O0.5
O0.4
1
1
1
1
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Table 8.
Bit
Symbol
Default
Output port 1 register (address 03h)
7
6
5
4
O1.7
O1.6
O1.5
O1.4
1
1
1
1
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
6.2.4 Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write is described in Section 7.1 and a register pair read is described in Section 7.2.
Table 9.
Bit
Symbol
Default
Polarity inversion port 0 register (address 04h)
7
6
5
4
3
N0.7
N0.6
N0.5
N0.4
N0.3
0
0
0
0
0
2
N0.2
0
1
N0.1
0
0
N0.0
0
Table 10.
Bit
Symbol
Default
Polarity inversion port 1 register (address 05h)
7
6
5
4
3
N1.7
N1.6
N1.5
N1.4
N1.3
0
0
0
0
0
2
N1.2
0
1
N1.1
0
0
N1.0
0
6.2.5 Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write is described in Section 7.1 and a register pair
read is described in Section 7.2.
Table 11.
Bit
Symbol
Default
Configuration port 0 register (address 06h)
7
6
5
4
3
C0.7
C0.6
C0.5
C0.4
C0.3
1
1
1
1
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
PCA9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 September 2012
© NXP B.V. 2012. All rights reserved.
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