74LVX4245MTC 查看數據表（PDF） - Fairchild Semiconductor

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74LVX4245MTC

8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

Fairchild Semiconductor 

Capacitance

Symbol

Parameter

Typ

CIN

Input Capacitance

4.5

CI/O

Input/Output

15

Capacitance

CPD

Power Dissipation

B→A

55

Capacitance (Note 10)

A→B

40

Note 10: CPD is measured at 10 MHz

8-Bit Dual Supply Translating Transceiver

The LVX4245 is a dual supply device capable of bidirec-

tional signal translation. This level shifting ability provides

an efficient interface between low voltage CPU local bus

with memory and a standard bus defined by 5V I/O levels.

The device control inputs can be controlled by either the

low voltage CPU and core logic or a bus arbitrator with 5V

I/O levels.

Manufactured on a sub-micron CMOS process, the

LVX4245 is ideal for mixed voltage applications such as

notebook computers using 3.3V CPU’s and 5V peripheral

devices.

Units

pF

pF

pF

pF

Conditions

VCC = Open

VCCA = 5.0V

VCCB = 3.3V

VCCA = 5.0V

VCCB = 3.3V

Power Up Considerations

To insure the system does not experience unnecessary ICC

current draw, bus contention, or oscillations during power

up, the following guidelines should be adhered to (refer to

Table 1):

• Power up the control side of the device first. This is the

VCCA.

• OE should ramp with or ahead of VCCA. This will help

guard against bus contention.

• The Transmit/Receive control pin (T/R) should ramp with

or ahead of VCCA, this will ensure that the A Port data

pins are configured as inputs. With VCCA receiving

power first, the A I/O Port should be configured as inputs

to help guard against bus contention and oscillations.

• A side data inputs should be driven to a valid logic level.

This will prevent excessive current draw.

The above steps will ensure that no bus contention or oscil-

lations, and therefore no excessive current draw occurs

during the power up cycling of these devices. These steps

will help prevent possible damage to the translator devices

and potential damage to other system components.

TABLE 1. Low Voltage Translator Power Up Sequencing Table

Device Type

VCCA

VCCB

T/R

OE

A Side

I/O

B Side

I/O

Floatable Pin

Allowed

5V

3V

ramp

ramp

logic

74LVX4245

outputs

No

(power up 1st) (power up 2nd)

with VCCA

with VCCA

0V or VCCA

Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual

Supply CMOS Translating Transceivers.

5

www.fairchildsemi.com

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