PCA9554CBS 查看數據表（PDF） - NXP Semiconductors.
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PCA9554CBS
NXP Semiconductors.
PCA9554CBS Datasheet PDF : 36 Pages
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NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
7.2 Read commands
To read data from the PCA9554B/PCA9554C, the bus master must first send the
PCA9554B/PCA9554C address with the least significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which
register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the
PCA9554B/PCA9554C (see Figure 9 and Figure 10).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
slave address(1)
SDA S 0 1 0 0 A2 A1 A0 0 A
COMMAND BYTE
A (cont.)
START condition
R/W acknowledge from slave
slave address(1)
data from register
(cont.) S 0 1 0 0 A2 A1 A0 1 A
DATA (first byte)
acknowledge from slave
data from register
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from slave
acknowledge
from master
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
STOP
condition
002aah126
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 9. Read from register
SCL 1 2 3 4 5 6 7 8 9
slave address(1)
data from port
data from port
no acknowledge
from master
SDA S 0 1 0 0 A2 A1 A0 1 A
DATA 1
A
DATA 4
1P
START condition
read from
port
data into
port
DATA 1
INT
tv(INT)
R/W acknowledge from slave
th(D)
DATA 2
DATA 3
tsu(D)
trst(INT)
acknowledge from master
DATA 4
STOP
condition
DATA 5
INT is cleared by
read from port
STOP not needed
to clear INT
002aah127
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 9).
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 10. Read Input port register
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 September 2012
© NXP B.V. 2012. All rights reserved.
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