PCA9554PW-T 查看數據表（PDF） - NXP Semiconductors.
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PCA9554PW-T Datasheet PDF : 35 Pages
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NXP Semiconductors
PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be
raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
data from
shift register
data from
shift register
write configuration
pulse
configuration
register
DQ
FF
CK Q
write pulse
read pulse
data from
shift register
write polarity
pulse
DQ
FF
CK
output port
register
Q1
100 kΩ
Q2
input port
register
DQ
FF
CK
polarity inversion
register
DQ
FF
CK
Remark: At power-on reset, all registers return to default values.
Fig 8. Simplified schematic of IO0 to IO7
output port
register data
VDD
IO0 to IO7
VSS
input port
register data
to INT
polarity inversion
register data
002aac493
PCA9554_9554A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 19 March 2013
© NXP B.V. 2013. All rights reserved.
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