PCA9555PW 查看數據表（PDF） - Philips Electronics

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PCA9555PW

16-bit I2C and SMBus I/O port with interrupt

Philips Electronics 

slave address

acknowledge

from slave

acknowledge

from slave

slave address

acknowledge

from slave

data from lower

or upper byte

of register

acknowledge

from master

S 0 1 0 0 A2 A1 A0 0 A

R/W

COMMAND BYTE

A S 0 0 1 0 A2 A1 A0 1 A MSB

DATA

LSB A

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

R/W

first byte

data from upper

or lower byte of

register

no acknowledge

from master

NOTE: Transfer can be stopped at any time by a STOP condition.

Figure 8. READ from register

MSB

DATA

last byte

LSB NA P

SU01463

SCL

123456789

I0.x

I1.x

I0.x

I1.x

SDA S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P

READ FROM PORT 0

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

tIV

tIR

SU01464

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9. READ input port register — scenario 1

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