PCF8558 查看數據表（PDF） - Philips Electronics
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PCF8558 Datasheet PDF : 24 Pages
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Philips Semiconductors
Universal LCD driver for small graphic
panels
Objective specification
PCF8558
COMMANDS
Display Control
BIT
PD
V
LOGIC 0
LOGIC 1
normal
power-down
horizontal addressing vertical addressing
Table 2 Display status
DISPLAY STATUS
Blank
Normal
All segments on
Inverse video
BITS
E
D
0
0
1
1
1
0
0
1
PD: POWER-DOWN
• All LCD outputs at VDD (display off)
• Bias generator off
• Power-on reset on, oscillator off (external clock still
possible)
• VLCD can be disconnected
• I2C-bus, RAM, commands, etc. still function in
power-down mode.
Set Address
Table 3 Y0, Y1 and Y2 define the Y address vector
address of the display RAM
Y2
Y1
Y0
LINE
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
Set X address
The X address points to the columns. The range of X is
0 to 100 (64H).
Reset function
After power-on the chip has the following state:
• Power-down mode (PD = 1)
• RAM undefined
• RAM X and Y address undefined
• Display control bits (except PD) undefined
• I2C-bus interface reset.
Note
If the chip is used with an external clock source, after
power-on, the chip requires at least 2 clock pulses to
ensure that an internal synchronous reset is carried out.
After the internal reset, the chip goes into power-down
mode (PD = 1). If the clock pulses are not supplied, and
the reset is not cleared, the chip cannot respond to
commands in the I2C bus.
In applications where the internal oscillator is used
(pin OSC = VDD), the oscillator starts after power-on.
As soon as the synchronous reset is cleared, the chip goes
into power-down mode, and the oscillator is stopped.
Table 4 Instructions: control byte, address
INSTRUCTION
Display control
X address
DB7
0
0
DB6
E
DB5
D
DB4 DB3 DB2
PD V Y2
X address
DB1
Y1
DB0
DESCRIPTION
Y0 Y address vector, display control
set column address
1998 Apr 07
10
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