PC85232-1 查看數據表（PDF） - NXP Semiconductors.

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PC85232-1

LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCF85132

LCD driver for low multiplex rates

6.2 Pin description

Table 3. Pin description

Symbol

Pin

SDAACK[1]

1 to 3

SDA[1]

4 to 6

SCL

7 to 9

CLK

10

VDD

SYNC

11 to 13

14

OSC

15

T1, T2, and T3

16, 17, and 18 to 20

A0 and A1

SA0

VSS[2]

VLCD

BP2 and BP0

S0 to S79

BP0, BP2, BP1, and BP3

S80 to S159

BP3 and BP1

21, 22

23

24 to 26

27 to 29

30, 31

32 to 111

112 to 115

116 to 195

196, 197

Description

I2C-bus acknowledge output

I2C-bus serial data input

I2C-bus serial clock input

clock input and output

supply voltage

cascade synchronization input and output

selection of internal or external clock

dedicated testing pins; to be tied to VSS in

application mode

subaddress inputs

I2C-bus slave address input

ground supply voltage

LCD supply voltage

LCD backplane outputs

LCD segment outputs

LCD backplane outputs

LCD segment outputs

LCD backplane outputs

[1] For most applications SDA and SDAACK are shorted together (see Section 12.2 on page 38).

[2] The substrate (rear side of the die) is wired to VSS and should be electrically isolated.

PCF85132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 23 November 2010

© NXP B.V. 2010. All rights reserved.

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