PC85133-1(2009) 查看數據表（PDF） - NXP Semiconductors.
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PC85133-1 Datasheet PDF : 41 Pages
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NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
• In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1 and 2 of three
successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not
recommended to use this bit in a display because of the difficult addressing. This last
bit may, if necessary, be controlled by an additional transfer to this address but care
should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
• In the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into
row 0, 1, 2 and 3 of two successive 4-bit RAM words.
display RAM addresses (columns) / segment outputs (S)
01234
75 76 77 78 79
0
display RAM bits
(rows) /
1
backplane outputs
(BP)
2
3
mgl750
Fig 9.
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs; and between the bits in a RAM word and the backplane outputs.
Display RAM bitmap
7.11 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer.
This allows the loading of an individual display data byte, or a series of display data bytes,
into any location of the display RAM. The sequence commences with the initialization of
the data pointer by the load-data-pointer command.
Following this command, an arriving data byte is stored at the display RAM address
indicated by the data pointer. The filling order is shown in Figure 10.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
• In static drive mode by eight
• In 1:2 multiplex drive mode by four
• In 1:3 multiplex drive mode by three
• In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer must be re-written prior to further RAM accesses.
PCF85133_1
Product data sheet
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
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