PC85133-1 查看數據表（PDF） - NXP Semiconductors.

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PC85133-1

Universal LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

6. Pinning information

6.1 Pinning

PCF85133

Universal LCD driver for low multiplex rates

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DDM

Viewed from active side. For mechanical details, see Figure 25.

Fig 2. Pin configuration for PCF85133

6.2 Pin description

Table 4. Pin description overview

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol

Pin

Description

SDAACK

1 to 3

I2C-bus acknowledge output

SDA

4 to 6

I2C-bus serial data input

SCL

7 to 9

I2C-bus serial clock input

CLK

10

clock input/output

VDD

SYNC

11 to 13

14

supply voltage

cascade synchronization input/output

OSC

15

oscillator select

FF

16

frame frequency select

A0, A1 and A2

17 to 19

subaddress input

SA0

20

I2C-bus slave address input

VSS[1]

VLCD

BP2, BP0, BP3 and BP1

21 to 23

ground supply voltage

24 to 26

LCD supply voltage

27, 28, 109 and 110 LCD backplane output

S0 to S79

29 to 108

LCD segment output

D1 to D9

-

dummy pads

[1] The substrate (rear side of the die) is at VSS potential and should be electrically isolated.

PCF85133

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 4 July 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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